125 lines
3.1 KiB
C++
125 lines
3.1 KiB
C++
#ifdef COMPILER_MSVC // Added by JE - 05-12-2009. Inline assembler instructions
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// have been changed to Intel format and (in the case of
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// cpuid) was replaced by the equivalent VC++ system call).
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#define _XOPEN_SOURCE 600
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#include <cstdlib>
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#include <stdint.h>
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#include <intrin.h> // Added by JE - 05-12-2009
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#include <pbd/fpu.h>
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#include <pbd/error.h>
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#include "i18n.h"
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using namespace PBD;
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using namespace std;
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FPU::FPU ()
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{
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unsigned long cpuflags = 0;
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_flags = (Flags)0;
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#ifndef ARCH_X86
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return;
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#else
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#ifndef USE_X86_64_ASM
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int cpuInfo[4];
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__cpuid (cpuInfo, 1);
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cpuflags = cpuInfo[3];
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/*
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__asm { // This is how the original section would look if converted to Intel syntax.
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// However, I have grave doubts about whether it's doing the right thing.
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// It seems as if the intention was to retrieve feature information from
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// the processor. However, feature information is returned in the ebx register
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// (if you believe Wikipedia) or in edx (if you believe Microsoft). Unfortunately,
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// both registers get ignored in the original code!! Confused?? Join the club!!
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mov eax, 1
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push ebx
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cpuid
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mov edx, 0
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pop ebx
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mov cpuflags, ecx // This can't be right, surely???
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}; */
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#else
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// Note that this syntax is currently still in AT&T format !
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asm volatile (
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"pushq %%rbx\n"
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"movq $1, %%rax\n"
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"cpuid\n"
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"movq %%rdx, %0\n"
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"popq %%rbx\n"
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: "=r" (cpuflags)
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:
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: "%rax", "%rcx", "%rdx", "memory"
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);
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#endif /* USE_X86_64_ASM */
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if (cpuflags & (1<<25)) {
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_flags = Flags (_flags | (HasSSE|HasFlushToZero));
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}
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if (cpuflags & (1<<26)) {
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_flags = Flags (_flags | HasSSE2);
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}
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if (cpuflags & (1 << 24)) {
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bool aligned_malloc = false; // Added by JE - 05-12-2009
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char* fxbuf = 0;
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// This section changed by JE - 05-12-2009
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#ifdef NO_POSIX_MEMALIGN
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#if defined(COMPILER_MSVC) || defined(COMPILER_MINGW) // All of these support '_aligned_malloc()'
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fxbuf = (char *) _aligned_malloc(512, 16); // (note that they all need at least MSVC runtime 7.0)
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aligned_malloc = true;
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#else
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fxbuf = (char *) malloc(512);
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#endif
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#else
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fxbuf = posix_memalign ((void**)&fxbuf, 16, 512);
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#endif
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// Verify that fxbuf is correctly aligned
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unsigned long buf_addr = (unsigned long)(void*)fxbuf;
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if ((0 == buf_addr) || (buf_addr % 16))
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error << _("cannot allocate 16 byte aligned buffer for h/w feature detection") << endmsg;
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else
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{
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memset(fxbuf, 0, 512); // Initialize the buffer !!! Added by JE - 12-12-2009
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__asm {
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mov eax, fxbuf
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fxsave [eax]
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};
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uint32_t mxcsr_mask = *((uint32_t*) &fxbuf[28]);
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/* if the mask is zero, set its default value (from intel specs) */
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if (mxcsr_mask == 0) {
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mxcsr_mask = 0xffbf;
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}
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if (mxcsr_mask & (1<<6)) {
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_flags = Flags (_flags | HasDenormalsAreZero);
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}
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if (aligned_malloc)
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_aligned_free (fxbuf);
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else
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free (fxbuf);
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}
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}
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#endif // ARCH_X86
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}
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FPU::~FPU ()
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{
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}
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#else // !COMPILER_MSVC
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const char* pbd_fpu = "original pbd/fpu.cc takes precedence over this file";
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#endif // COMPILER_MSVC
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