By supporting FMA extension, the number of instruction needed for multiply accumulate to mix channels are reduced. Since, this extension has been around since middle of 2012, more computers have this instruction set available.
330 lines
8.1 KiB
C++
330 lines
8.1 KiB
C++
/*
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* Copyright (C) 2007-2016 Paul Davis <paul@linuxaudiosystems.com>
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* Copyright (C) 2009-2012 David Robillard <d@drobilla.net>
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* Copyright (C) 2013-2015 John Emmas <john@creativepost.co.uk>
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* Copyright (C) 2015-2019 Robin Gareus <robin@gareus.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "libpbd-config.h"
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#define _XOPEN_SOURCE 600
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#include <cstring> // for memset
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#include <cstdlib>
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#include <stdint.h>
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#include <assert.h>
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#ifdef PLATFORM_WINDOWS
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#include <intrin.h>
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#endif
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#ifdef ARM_NEON_SUPPORT
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/* Needed for ARM NEON detection */
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#include <sys/auxv.h>
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#include <asm/hwcap.h>
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#endif
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#include "pbd/compose.h"
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#include "pbd/fpu.h"
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#include "pbd/error.h"
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#include "pbd/i18n.h"
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using namespace PBD;
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using namespace std;
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FPU* FPU::_instance (0);
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#if ( (defined __x86_64__) || (defined __i386__) || (defined _M_X64) || (defined _M_IX86) ) // ARCH_X86
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#ifndef PLATFORM_WINDOWS
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/* use __cpuid() as the name to match the MSVC/mingw intrinsic */
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static void
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__cpuid(int regs[4], int cpuid_leaf)
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{
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asm volatile (
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#if defined(__i386__)
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"pushl %%ebx;\n\t"
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#endif
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"cpuid;\n\t"
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"movl %%eax, (%1);\n\t"
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"movl %%ebx, 4(%1);\n\t"
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"movl %%ecx, 8(%1);\n\t"
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"movl %%edx, 12(%1);\n\t"
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#if defined(__i386__)
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"popl %%ebx;\n\t"
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#endif
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:"=a" (cpuid_leaf) /* %eax clobbered by CPUID */
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:"S" (regs), "a" (cpuid_leaf)
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:
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#if !defined(__i386__)
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"%ebx",
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#endif
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"%ecx", "%edx", "memory");
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}
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#endif /* !PLATFORM_WINDOWS */
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#ifndef HAVE_XGETBV // Allow definition by build system
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#if defined(__MINGW32__) && defined(__MINGW64_VERSION_MAJOR) && __MINGW64_VERSION_MAJOR >= 5
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#define HAVE_XGETBV
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#elif defined(_MSC_VER) && _MSC_VER >= 1600
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// '_xgetbv()' was only available from VC10 onwards
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#define HAVE_XGETBV
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#endif
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#endif
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#ifndef HAVE_XGETBV
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#ifdef COMPILER_MSVC
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// '_xgetbv()' was only available from VC10 onwards
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__declspec(noinline) static uint64_t
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_xgetbv (uint32_t xcr)
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{
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return 0;
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// N.B. The following would probably work for a pre-VC10 build,
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// although it might suffer from optimization issues. We'd need
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// to place this function into its own (unoptimized) source file.
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__asm {
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mov ecx, [xcr]
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__asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0 /*xgetbv*/
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}
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}
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#else
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static uint64_t
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_xgetbv (uint32_t xcr)
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{
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#ifdef __APPLE__
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/* it would be nice to make this work on OS X but as long we use veclib,
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we don't really need to know about SSE/AVX on that platform.
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*/
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return 0;
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#else
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uint32_t eax, edx;
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__asm__ volatile ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (xcr));
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return (static_cast<uint64_t>(edx) << 32) | eax;
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#endif
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}
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#endif /* !COMPILER_MSVC */
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#endif /* !HAVE_XGETBV */
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#endif /* ARCH_X86 */
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#ifndef _XCR_XFEATURE_ENABLED_MASK
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#define _XCR_XFEATURE_ENABLED_MASK 0
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#endif
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FPU*
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FPU::instance()
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{
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if (!_instance) {
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_instance = new FPU;
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}
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return _instance;
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}
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void
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FPU::destroy ()
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{
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delete _instance;
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_instance = 0;
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}
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FPU::FPU ()
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: _flags ((Flags) 0)
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{
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if (_instance) {
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error << _("FPU object instantiated more than once") << endmsg;
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}
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if (getenv("ARDOUR_FPU_FLAGS")) {
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_flags = Flags (atoi (getenv("ARDOUR_FPU_FLAGS")));
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return;
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}
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#ifdef ARM_NEON_SUPPORT
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# ifdef __aarch64__
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/* all armv8+ features NEON used in arm_neon_functions.cc */
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_flags = Flags(_flags | HasNEON);
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# elif defined __arm__
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if (getauxval(AT_HWCAP) & HWCAP_NEON) {
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_flags = Flags(_flags | HasNEON);
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}
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# endif
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#endif
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#if !( (defined __x86_64__) || (defined __i386__) || (defined _M_X64) || (defined _M_IX86) ) // !ARCH_X86
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/* Non-Intel architecture, nothing to do here */
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return;
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#else
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/* Get the CPU vendor just for kicks
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*
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* __cpuid with an InfoType argument of 0 returns the number of
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* valid Ids in CPUInfo[0] and the CPU identification string in
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* the other three array elements. The CPU identification string is
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* not in linear order. The code below arranges the information
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* in a human readable form. The human readable order is CPUInfo[1] |
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* CPUInfo[3] | CPUInfo[2]. CPUInfo[2] and CPUInfo[3] are swapped
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* before using memcpy to copy these three array elements to cpu_string.
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*/
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int cpu_info[4];
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char cpu_string[48];
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string cpu_vendor;
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__cpuid (cpu_info, 0);
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int num_ids = cpu_info[0];
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std::swap(cpu_info[2], cpu_info[3]);
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memcpy(cpu_string, &cpu_info[1], 3 * sizeof(cpu_info[1]));
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cpu_vendor.assign(cpu_string, 3 * sizeof(cpu_info[1]));
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info << string_compose (_("CPU vendor: %1"), cpu_vendor) << endmsg;
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if (num_ids > 0) {
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/* Now get CPU/FPU flags */
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__cpuid (cpu_info, 1);
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if ((cpu_info[2] & (1<<27)) /* OSXSAVE */ &&
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(cpu_info[2] & (1<<28) /* AVX */) &&
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((_xgetbv (_XCR_XFEATURE_ENABLED_MASK) & 0x6) == 0x6)) { /* OS really supports XSAVE */
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info << _("AVX-capable processor") << endmsg;
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_flags = Flags (_flags | (HasAVX));
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}
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if (cpu_info[2] & (1<<12) /* FMA */) {
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info << _("AVX with FMA capable processor") << endmsg;
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_flags = Flags (_flags | (HasFMA));
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}
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if (cpu_info[3] & (1<<25)) {
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_flags = Flags (_flags | (HasSSE|HasFlushToZero));
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}
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if (cpu_info[3] & (1<<26)) {
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_flags = Flags (_flags | HasSSE2);
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}
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/* Figure out CPU/FPU denormal handling capabilities */
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if (cpu_info[3] & (1 << 24)) {
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char** fxbuf = 0;
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/* DAZ wasn't available in the first version of SSE. Since
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setting a reserved bit in MXCSR causes a general protection
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fault, we need to be able to check the availability of this
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feature without causing problems. To do this, one needs to
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set up a 512-byte area of memory to save the SSE state to,
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using fxsave, and then one needs to inspect bytes 28 through
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31 for the MXCSR_MASK value. If bit 6 is set, DAZ is
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supported, otherwise, it isn't.
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*/
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#ifndef HAVE_POSIX_MEMALIGN
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# ifdef PLATFORM_WINDOWS
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fxbuf = (char **) _aligned_malloc (sizeof (char *), 16);
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assert (fxbuf);
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*fxbuf = (char *) _aligned_malloc (512, 16);
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assert (*fxbuf);
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# else
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# warning using default malloc for aligned memory
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fxbuf = (char **) malloc (sizeof (char *));
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assert (fxbuf);
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*fxbuf = (char *) malloc (512);
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assert (*fxbuf);
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# endif
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#else
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(void) posix_memalign ((void **) &fxbuf, 16, sizeof (char *));
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assert (fxbuf);
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(void) posix_memalign ((void **) fxbuf, 16, 512);
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assert (*fxbuf);
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#endif
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memset (*fxbuf, 0, 512);
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#ifdef COMPILER_MSVC
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char *buf = *fxbuf;
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__asm {
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mov eax, buf
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fxsave [eax]
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};
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#else
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asm volatile (
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"fxsave (%0)"
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:
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: "r" (*fxbuf)
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: "memory"
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);
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#endif
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uint32_t mxcsr_mask = *((uint32_t*) &((*fxbuf)[28]));
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/* if the mask is zero, set its default value (from intel specs) */
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if (mxcsr_mask == 0) {
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mxcsr_mask = 0xffbf;
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}
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if (mxcsr_mask & (1<<6)) {
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_flags = Flags (_flags | HasDenormalsAreZero);
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}
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#if !defined HAVE_POSIX_MEMALIGN && defined PLATFORM_WINDOWS
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_aligned_free (*fxbuf);
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_aligned_free (fxbuf);
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#else
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free (*fxbuf);
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free (fxbuf);
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#endif
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}
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/* finally get the CPU brand */
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__cpuid (cpu_info, 0x80000000);
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const int parameter_end = 0x80000004;
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string cpu_brand;
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if (cpu_info[0] >= parameter_end) {
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char* cpu_string_ptr = cpu_string;
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for (int parameter = 0x80000002; parameter <= parameter_end &&
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cpu_string_ptr < &cpu_string[sizeof(cpu_string)]; parameter++) {
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__cpuid(cpu_info, parameter);
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memcpy(cpu_string_ptr, cpu_info, sizeof(cpu_info));
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cpu_string_ptr += sizeof(cpu_info);
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}
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cpu_brand.assign(cpu_string, cpu_string_ptr - cpu_string);
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info << string_compose (_("CPU brand: %1"), cpu_brand) << endmsg;
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}
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}
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#endif /* !ARCH_X86 */
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}
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FPU::~FPU ()
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{
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}
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