Paul Davis
a556546291
git-svn-id: svn://localhost/ardour2/branches/3.0@11079 d708f5d6-7413-0410-9779-e7cbd77b26cf
121 lines
2.4 KiB
C++
121 lines
2.4 KiB
C++
#include "libpbd-config.h"
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#define _XOPEN_SOURCE 600
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#include <cstring> // for memset
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#include <cstdlib>
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#include <stdint.h>
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#include "pbd/fpu.h"
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#include "pbd/error.h"
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#include "i18n.h"
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using namespace PBD;
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using namespace std;
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FPU::FPU ()
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{
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unsigned long cpuflags = 0;
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_flags = Flags (0);
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#if !( (defined __x86_64__) || (defined __i386__) ) // !ARCH_X86
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return;
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#else
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#ifndef _LP64 //USE_X86_64_ASM
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asm volatile (
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"mov $1, %%eax\n"
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"pushl %%ebx\n"
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"cpuid\n"
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"movl %%edx, %0\n"
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"popl %%ebx\n"
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: "=r" (cpuflags)
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:
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: "%eax", "%ecx", "%edx"
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);
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#else
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/* asm notes: although we explicitly save&restore rbx, we must tell
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gcc that ebx,rbx is clobbered so that it doesn't try to use it as an intermediate
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register when storing rbx. gcc 4.3 didn't make this "mistake", but gcc 4.4
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does, at least on x86_64.
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*/
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asm volatile (
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"pushq %%rbx\n"
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"movq $1, %%rax\n"
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"cpuid\n"
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"movq %%rdx, %0\n"
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"popq %%rbx\n"
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: "=r" (cpuflags)
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:
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: "%rax", "%rbx", "%rcx", "%rdx"
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);
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#endif /* USE_X86_64_ASM */
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if (cpuflags & (1<<25)) {
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_flags = Flags (_flags | (HasSSE|HasFlushToZero));
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}
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if (cpuflags & (1<<26)) {
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_flags = Flags (_flags | HasSSE2);
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}
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if (cpuflags & (1 << 24)) {
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char* fxbuf = 0;
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/* DAZ wasn't available in the first version of SSE. Since
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setting a reserved bit in MXCSR causes a general protection
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fault, we need to be able to check the availability of this
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feature without causing problems. To do this, one needs to
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set up a 512-byte area of memory to save the SSE state to,
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using fxsave, and then one needs to inspect bytes 28 through
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31 for the MXCSR_MASK value. If bit 6 is set, DAZ is
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supported, otherwise, it isn't.
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*/
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#ifdef NO_POSIX_MEMALIGN
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if ((fxbuf = (char *) malloc(512)) == 0)
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#else
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if (posix_memalign ((void**)&fxbuf, 16, 512))
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#endif
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{
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error << _("cannot allocate 16 byte aligned buffer for h/w feature detection") << endmsg;
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} else {
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memset (fxbuf, 0, 512);
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asm volatile (
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"fxsave (%0)"
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:
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: "r" (fxbuf)
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: "memory"
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);
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uint32_t mxcsr_mask = *((uint32_t*) &fxbuf[28]);
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/* if the mask is zero, set its default value (from intel specs) */
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if (mxcsr_mask == 0) {
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mxcsr_mask = 0xffbf;
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}
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if (mxcsr_mask & (1<<6)) {
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_flags = Flags (_flags | HasDenormalsAreZero);
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}
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free (fxbuf);
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}
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}
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#endif
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}
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FPU::~FPU ()
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{
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}
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