Align the address of the pointer to the fxsave block to a 16-byte boundary (as well as the pointer itself), which the internets seem to suggest is required.
git-svn-id: svn://localhost/ardour2/branches/3.0@12313 d708f5d6-7413-0410-9779-e7cbd77b26cf
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@ -4,6 +4,7 @@
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#include <cstring> // for memset
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#include <cstdlib>
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#include <stdint.h>
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#include <assert.h>
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#include "pbd/fpu.h"
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#include "pbd/error.h"
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@ -67,7 +68,7 @@ FPU::FPU ()
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if (cpuflags & (1 << 24)) {
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char* fxbuf = 0;
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char** fxbuf = 0;
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/* DAZ wasn't available in the first version of SSE. Since
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setting a reserved bit in MXCSR causes a general protection
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@ -80,24 +81,27 @@ FPU::FPU ()
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*/
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#ifdef NO_POSIX_MEMALIGN
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if ((fxbuf = (char *) malloc(512)) == 0)
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fxbuf = (char **) malloc (sizeof (char *));
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assert (fxbuf);
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*fxbuf = (char *) malloc (512);
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assert (*fxbuf);
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#else
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if (posix_memalign ((void**)&fxbuf, 16, 512))
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posix_memalign ((void **) &fxbuf, 16, sizeof (char *));
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assert (fxbuf);
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posix_memalign ((void **) fxbuf, 16, 512);
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assert (*fxbuf);
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#endif
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{
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error << _("cannot allocate 16 byte aligned buffer for h/w feature detection") << endmsg;
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} else {
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memset (fxbuf, 0, 512);
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memset (*fxbuf, 0, 512);
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asm volatile (
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"fxsave (%0)"
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:
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: "r" (fxbuf)
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: "r" (*fxbuf)
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: "memory"
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);
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uint32_t mxcsr_mask = *((uint32_t*) &fxbuf[28]);
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uint32_t mxcsr_mask = *((uint32_t*) &((*fxbuf)[28]));
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/* if the mask is zero, set its default value (from intel specs) */
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@ -109,9 +113,9 @@ FPU::FPU ()
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_flags = Flags (_flags | HasDenormalsAreZero);
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}
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free (*fxbuf);
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free (fxbuf);
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}
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}
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#endif
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}
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